module decode_unit
(
	input wire sys_clk,
	input wire sys_rst_n,
	input wire decode_en,
	input wire [15:0] instruct_word,
	
	output reg decode_done,
	output reg [4:0] op_code,
	output reg [2:0] reserve_bit,
	output reg [7:0] op_rand
);

always @(posedge sys_clk or negedge sys_rst_n)
	if (sys_rst_n == 1'b0)
	begin
		decode_done <= 1'b0;
		op_code <= 5'h0;
		reserve_bit <= 3'h0;
		op_rand <= 8'h0;
	end
	else if (decode_en == 1'b1)
	begin
		decode_done <= 1'b1;
		op_code <= instruct_word[15:11];
		reserve_bit <= 3'h0;
		op_rand <= instruct_word[7:0];
	end
	else
	begin
		decode_done <= 1'b0;
		op_code <= op_code;
		reserve_bit <= reserve_bit;
		op_rand <= op_rand;
	end

endmodule